Thermal Guard-Banding
Stephen Crosher, CEO of Moortec, talks with Semiconductor Engineering about the impact of more accurate measurements on power, performance and reliability of designs from 40nm all the way down to 3nm.
View ArticleNew Design Approaches At 7/5nm
The race to build chips with a multitude of different processing elements and memories is making it more difficult to design, verify and test these devices, particularly when AI and leading-edge...
View ArticleMulti-Physics At 5/3nm
Joao Geada, chief technologist at ANSYS, talks about why timing, process, voltage, and temperature no longer can be considered independently of each other at the most advanced nodes, and why it becomes...
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Low Power Meets Variability At 7/5nm
Power-related issues are beginning to clash with process variation at 7/5nm, making timing closure more difficult and resulting in re-spins caused by unexpected errors and poor functional yield....
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Why Chips Are Getting Noisier
In the past, designers only had to worry about noise for sensitive analog portions of a design. Digital circuitry was immune. But while noise gets worse at newer process nodes, staying at 28nm does not...
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Less Margin, More Respins, And New Markets
Semiconductor Engineering sat down to discuss the impact of multi-physics and new market applications on chip design with John Lee, general manager and vice president of ANSYS’ Semiconductor Business...
View ArticleMonitoring Heat On AI Chips
Stephen Crosher, CEO of Moortec, talks about monitoring temperature differences on-chip in AI chips and how to make the most of the power that can be delivered to a device and why accuracy is so...
View ArticleCurvilinear Full-Chip ILT
Leo Pang, chief product officer and executive vice president at D2S, talks about the speed improvements with full-chip inverse lithography technology, why it is so critical in stitching together large...
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The Challenge Of Defining Worst Case
Worst case conditions within a chip are impossible to define. But what happens if you missed a corner case that causes chip failure? As the semiconductor market becomes increasingly competitive —...
View ArticleThermal Guardbanding
Stephen Crosher, CEO of Moortec, looks at the causes of thermal runaway in racks of servers and explains why accurate temperature measurement in AI and advanced-node chips is more critical, and what...
View ArticleAnalog Simulation At 7/5/3nm
Hany Elhak, group director of product management at Cadence, talks with Semiconductor Engineering about analog circuit simulation at advanced nodes, why process variation is an increasing problem, the...
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Wrestling With Variation In Advanced Node Designs
Variation is becoming a major headache at advanced nodes, and issues that used to be dealt with in the fab now must be dealt with on the design side, as well. What is fundamentally changing is that...
View ArticleCustom Designs, Custom Problems
Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at...
View ArticlePerformance and Power Tradeoffs At 7/5nm
Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at...
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Brute-Force Analysis Not Keeping Up With IC Complexity
Much of the current design and verification flow was built on brute force analysis, a simple and direct approach. But that approach rarely scales, and as designs become larger and the number of...
View ArticleNext-Gen Design Challenges
As more heterogeneous chips and different types of circuitry are designed into one system, that all needs to be simulated, verified and validated before tape-out. Aveek Sarkar, vice president of...
View ArticleDo We Have An IC Model Crisis?
Models are critical for IC design. Without them, it’s impossible to perform analysis, which in turn limits optimizations. Those optimizations are especially important as semiconductors become more...
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Designing Chips For Test Data
Collecting data to determine the health of a chip throughout its lifecycle is becoming necessary as chips are used in more critical applications, but being able to access that data isn’t always so...
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Reliability Concerns Shift Left Into Chip Design
Demand for lower defect rates and higher yields is increasing, in part because chips are now being used for safety- and mission-critical applications, and in part because it’s a way of offsetting...
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