Experts At The Table: The Growing Signoff Headache
By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product...
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Power Grid Analysis
By Marko Chew Introduction Power grids (PGs) have consumed an increasingly larger percentage of routing resources in recent process node generations, due to lower maximum current limits imposed by the...
View ArticleNew Approaches To Low Power Design
While Moore’s Law continues to drive feature size reduction and complexity, a whole separate part of the industry is growing up around vertical markets in the IoT. While these two worlds may be...
View ArticleOne On One: John Lee
John Lee, general manager and vice president of Ansys—and the former CEO of data analytics firm Gear Design Solutions, which Ansys acquired in September—sat down with Semiconductor Engineering to talk...
View ArticleHave Margins Outlived Their Usefulness?
To automate the process of solving complex design problems, the traditional approach has been to partition them into smaller, manageable tasks. For each task, we have built the best possible solution...
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Big Data Meets Chip Design
The amount of data being handled in chip design is growing significantly at each new node, prompting chipmakers to begin using some of the same concepts, technologies and algorithms used in data...
View ArticleOptimization Challenges For 10nm And 7nm
Optimization used to be a simple timing against area tradeoff, but not anymore. As we go to each new node the tradeoffs become more complicated, involving additional aspects of the design that used to...
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Tech Talk: Power Signoff
Ansys’ Aveek Sarkar the challenges of power signoff at advanced process nodes, the impact of over-design, and what’s necessary for sufficient coverage.
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What Can Be Cut From A Design?
A long-standing approach of throwing everything into a chip increasingly is being replaced by a focus on what can be left out it. This shift is happening at every level, from the initial design to...
View ArticleWorst-Case Results Causing Problems
The ability of design tools to identify worst-case scenarios has allowed many chipmakers to flag potential issues well ahead of tapeout, but as process geometries shrink that approach is beginning to...
View ArticleTrimming Waste In Chips
Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed? When people are asked that question they either get defensive or they see it as an...
View ArticleTech Talk: 7nm Process Variation
Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond.
View ArticleTech Talk: On-Chip Variation
Raymond Nijssen, vice president of systems engineering at Achronix, discusses on-chip and process variation at 7nm and 5nm, the role of embedded FPGAs, and how to reduce margin and pessimistic designs.
View ArticleWhy Inductance Is Good for Area, Power and Performance
By Magdy Abadir and Yehea Ismail For chips designed at advanced technology nodes, interconnect is the dominant contributor towards delay, power consumption, and reliability. Major interconnects such as...
View ArticleTech Talk: 7/5/3nm Signoff
Anand Raman, director of technical marketing at Helic, explains what’s needed to improve confidence in designs at the most advanced process nodes.
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Near-Threshold Issues Deepen
Complex issues stemming from near-threshold computing, where the operating voltage and threshold voltage are very close together, are becoming more common at each new node. In fact, there are reports...
View Article7nm Design Challenges
Ty Garibay, CTO at ArterisIP, talks about the challenges of moving to 7nm, who’s likely to head there, how long it will take to develop chips at that node, and why it will be so expensive. This also...
View ArticleIn-Design Power Rail Analysis
Tech Talk: Kenneth Chang, senior staff product marketing manager at Synopsys, talks about what can go wrong with power at advanced nodes and why in-design power rail analysis works best early in the...
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5nm Design Progress
Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new...
View ArticleInferencing In Hardware
Cheng Wang, senior vice president of engineering at Flex Logix, examines shifting neural network models, how many multiply-accumulates are needed for different applications, and why programmable neural...
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